SEMICONDUCTOR STORAGE DEVICE, TEST METHOD THEREFOR, AND TEST CIRCUIT THEREFOR

摘要

A test method and test circuit capable of performing operational tests when the time interval between a refresh operation and a read/write operation is compulsorily shortened. The timings of the read/write operations in the normal operation and test modes are established based on address transition detecting signals ATD. The timing of the refresh operation in the normal operation mode is established based on a normal refresh pulse signal REF generated by a refresh pulse generating circuit (60) in response to a timing signal TM generated by a timer circuit (50). The timing of the refresh operation in the test mode is established based on a first test refresh pulse generation signal (TREF1) generated by a first test refresh pulse generating circuit (62) in response to an address transition detecting signal ATD. The generation timing of the first test refresh pulse generation signal (TREF1) is controlled, thereby allowing the read/write operation and refresh operation to occur at a predetermined time interval.