| 摘要 |
<p>The refreshing of the memory cells is periodically executed by use of a refresh timer, and the collision between a memory access and a memory refresh is avoided. During a memory access, a one-shot pulse from an OS circuit (161) sets an F/F (163), and a memory access request is inputted to a memory access pulse generating circuit (171) via a NOR gate (167), and a latch control signal (LC) and an enable signal (REN) are outputted. When a refresh request form a refresh timer is inputted to an AND gate (168) during the memory access, the output of the NOR gate (167) is “L” level, so that the refresh request is blocked by the AND gate (168). Thereafter, when the latch control signal (LC) becomes “L” level, F/Fs (163,164,165) are reset and the output of the NOR gate (167) becomes “H” level, so that the refresh request is inputted to a refresh pulse generating circuit (170) and a refresh enable signal (RERF) is outputted.</p> |
