Semiconductor memory system having dynamically delayed timing for high-speed data transfers

摘要

A timing system for controlling timing of data transfers within a semiconductor memory system is provided. The timing system includes a programming circuit for generating a bias signal, wherein the bias signal is biased in accordance with an incoming data transfer address corresponding to a memory address of the memory system, and a delay module for receiving the bias signal and generating an output clock signal, wherein the output clock signal is delayed in accordance with the bias signal.