发明名称 MULTIPLIER
摘要 <p>A conventional multiplier comprising a MOS transistor has had the problem that a complicated correcting circuit must be added in an output section or the like to compensate for the fluctuation or the like of a bias voltage, and that power consumption increases along with an increase in circuit scale. A multiplier comprises NMOS transistors (3, 4, 5) and constant voltage sources (6, 9, 12) connected to the gates of the NMOS transistors (3, 4, 5), respectively. The voltage value of the constant voltage source (9) is equalized with that of the constant voltage source (12), so that the NMOS transistor (4) and the NMOS transistor (5) are formed to be the same.</p>
申请公布号 WO2003056497(P1) 申请公布日期 2003.07.10
申请号 JP2002012557 申请日期 2002.11.29
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