发明名称 APPROXIMATE STATE CONTROL MECHANISM
摘要 A data packet switching system having a central controller and a number of peripheral controllers each incorporating at least one queue for storing packets of information received from a peripheral data packet source. Each queue in each peripheral controller includes a queue size detection logic adapted to communicate to the central controller the approximate state of the size of the corresponding queue. The scale for the approximate state being arranged to be empty, nearly empty, active, busy, very busy, nearly full and full.
申请公布号 EP1142220(B1) 申请公布日期 2003.07.09
申请号 EP19990959604 申请日期 1999.12.14
申请人 XYRATEX TECHNOLOGY LIMITED 发明人 JOHNSON, IAN DAVID;HOWARTH, PAUL
分类号 H04L12/70;H04L12/801;H04L12/835;H04L12/935;H04L12/937;H04L12/939;(IPC1-7):H04L12/56 主分类号 H04L12/70
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