| 摘要 |
In a semiconductor memory device that includes memory cell array banks, memory cell array blocks in each memory cell array bank, partial blocks in each memory cell array block, data input/output line pairs connected to the partial blocks, and a predetermined number of redundant partial blocks connected to a predetermined number of redundant data input/output line pairs, the semiconductor memory device further includes an address setting circuit to set a redundant control signal and a defect address of each of the memory cell array blocks, decoder and shifting control signal generating circuits to generate shifting control signals to control shifting of the data input/output line pairs and the predetermined number of redundant data input/output line pairs by decoding the redundant control signal and the defective address, and switching circuits for routing data through data input/output line pairs adjacent to a corresponding data input/output line pairs in response to each of the shifting control signals. Therefore, the semiconductor memory device can generate the shifting control signals dynamically to column cycle and can construct a redundancy circuit with a small number of fuses.
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