| 摘要 |
PURPOSE: A delay lock loop circuit is provided to reduce the time required to synchronize the external clock signal with the inner clock signal when the inner clock signal is delayed over 90° in comparison with the external clock signal. CONSTITUTION: A delay lock loop circuit includes a delay line(201), a high speed mode phase detection block(202) and a high speed mode delay control block(203). The high speed mode phase detection block(202) includes a 90° shifter(208), a pair of phase detectors(206), an inverter(210) and a 2 x 4 counter(214). The high speed mode delay control block(203) includes a shift register(204) and a counter(216). In the delay lock loop circuit, if the second control signal is received from the high speed mode phase detector block(202), the delay of the external clock signal becomes 90° at the delay line(201), if the third control signal is received, becomes 180°, and if the fourth control signal is received, becomes 270°.
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