发明名称 CIRCUIT FOR TESTING SPEED OF DRAM AND METHOD FOR TESTING THE SAME
摘要 PURPOSE: A circuit for testing the speed of DRAM and a method for testing the same are provided to accurately screen products having a bad speed characteristics since the speed characteristics of the DRAM is measured by varying the external clock frequency. CONSTITUTION: A circuit for testing the speed of DRAM includes an asynchronous DRAM block(21), a latch block(22), a test circuit block(23) and an output port(24). In the circuit, the latch block(22) stores the output data outputted from the asynchronous DRAM block(21) with being synchronized to the external clock signal which is applied by being varied. The test circuit block(23) tests the output data of the synchronous DRAM block(21) stored at the latch block(22) if the speed characteristics is satisfied with the applied external clock signal. And, if the speed characteristics is satisfied with the applied external clock signal, the output port(24) outputs the test value of the test circuit block(23).
申请公布号 KR20030058820(A) 申请公布日期 2003.07.07
申请号 KR20020000038 申请日期 2002.01.02
申请人 HYNIX SEMICONDUCTOR INC. 发明人 OH, MYEONG GYU
分类号 G11C29/00;(IPC1-7):G11C29/00 主分类号 G11C29/00
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