| 摘要 |
PURPOSE: A half adder circuit is provided to improve an economical efficiency and execute a high speed switching operation by reducing the number of gates. CONSTITUTION: A first CMOS inverter(20) is constituted between a carry terminal(C) and a sum terminal(S), operated by receiving a signal(A) of the first input signal terminal, and outputs the second input signal(B) to the carry terminal(C) or a sum terminal(S) in accordance with the first input signal(A). The first switching element is constituted between the first input signal terminal and the carry terminal(C) for a diode connection to the first input signal terminal. The second CMOS inverter(21) is constituted between a power voltage terminal(VCC) and an earthing voltage terminal(VSS) and operated by receiving the second input signal. The second switching element is constituted between the second CMOS inverter(21) and the sum terminal(S) and operated by receiving the first input signal. The first CMOS inverter(20) comprises the first n-MOS transistor(N1) being contacted with the carry terminal(C) and the first p-MOS transistor(P1) being contacted with the sum terminal(S). The first switching element comprises the second p-MOS transistor(P2). The second switching element comprises the second n-MOS transistor(N2).
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