| 摘要 |
PURPOSE: A synchronous semiconductor memory device is provided to further simplify the hardware configuration of the data input path so as to implement the parallel test for supplying all of the solid pattern mode and the checker board pattern mode. CONSTITUTION: A synchronous semiconductor memory device includes a plurality of DQ pins(200), a plurality of bit lines(240), a data input structure(210) placed between the plurality of DQ pins(200) and the plurality of bit lines(240), a plurality of multiplexers(221,222) and a plurality of data input driving blocks(230). The test mode rising mode is inputted to the multiplexer(221) corresponding to the representative DQ pin(DQ0) and the sub DQ pin(DQ2), whereas the test mode rising data is inputted to the multiplexer(222) corresponding to the representative DQ pin(DQ0) and the sub DQ pin(DQ1,DQ3).
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