发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY
摘要 Inputs of two buffer circuits which constitute a latch circuit receive different voltages due to a capacitance coupling effect of ferroelectric capacitors or capacitance division of the ferroelectric capacitors, before connected with power source. After the power turns on, a switch control circuit activates switch control signals when a first plate voltage rises to a predetermined voltage. Switch circuits turn on in response to the activation of the switch control signals, and connect power source terminals of the buffer circuits to a power source line. At this time, input voltages of the buffer circuits are different from each other, and therefore, logic data is written into the latch circuit according to each of the input voltages. As a result of this, data held in the latch circuit before turning-off of the power can be reproduced without fail.
申请公布号 KR20030057294(A) 申请公布日期 2003.07.04
申请号 KR20020063757 申请日期 2002.10.18
申请人 发明人
分类号 G11C11/22;G11C11/41;G11C11/412;G11C14/00 主分类号 G11C11/22
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