| 摘要 |
PURPOSE: A clock synchronizer is provided to reduce the synchronization time for the external clock signals of the ultra low frequency, the low frequency and the high frequency by using an auxiliary delay circuit. CONSTITUTION: A clock synchronizer includes a clock buffer(10), a variable delay line(20), an auxiliary delay block(30), a programmable divider(40), a dummy variable delay line(50), a dummy auxiliary delay block(60), a dummy input and output data buffer(70), a dummy clock buffer(80), a compensation delay block(90), a dummy programmable divider(100), a phase detection block(110) and a shift register(120). In the clock synchronizer, the variable delay line(20) outputs the inner clock signal by delaying the external clock signal inputted from outside by a predetermined time. An auxiliary delay block(30) change a delay route of an internal clock according to a frequency of the external clock. The programmable divider(40) differently sets the dividing ratio in response to the frequency of the external clock signal. The phase detection block(110) compares the phase of the output clock signal of the dummy circuit with the output clock signal of the programmable divider(40). And, the shift register(120) controls the delay time of the variable delay line in response to the output signal of the phase detection block(110).
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