HIGH SPEED SDRAM CONTROL DEVICE BY USING BANK RECOGNITION AND METHOD FOR THE SAME

摘要

PURPOSE: A high speed SDRAM control device by using a bank recognition and a method for the same are provided to remove the open and close processes of the undesired banks by identifying the bank accessed to the read or the write operation, thereby reducing the number of cycles per operation and minimizing the delay. CONSTITUTION: A high speed SDRAM control device by using a bank recognition includes an SDRAM(100), a processor(200) and a control device(300). The SDRAM(100) includes a command interpretation block(110) and an address register(120). The control device(300) includes a processor interface block(310), an SDRAM interface block(320) provided with a command signal generation block(322), a bank signal generation block(324) and an address signal generation block(326), an address interpretation block(330) and a command memory(340). In the high speed SDRAM control device, the address interpretation block(330) compares the bank address of the SDRAM requested to the read or write command from the processor(200) with the bank address of the SDRAM during the performing the read or write command and performs the precharge command and the bank activation command by the SDRAM interface block(320).