发明名称 IMAGE PROCESSING APPARATUS
摘要 <p><P>PROBLEM TO BE SOLVED: To provide an image processing apparatus capable of applying decoding processing to an image encoded by a plurality of encoding processes at a high-speed. <P>SOLUTION: The image processing apparatus applies decoding processing to image data encoded by a plurality of encoding processes by each of pixel blocks being divisions of an image, and is provided with: FIFO memories 22, 24, 26, 28 that store the received pixel blocks by each encoding method; a decoding section 30 connected to the memories and applying decode processing to the encoded data in accordance with the encoding method; and a selector 35 that selects any of corresponding processing sections (DC processing section 31, AOT (adaptive orthogonal transform) processing section 32, LUM processing section 33, and ACP (AC component predictive) processing section 34) on the basis of control information denoting the encoding method and attached to each of the encoded data and providing an external output of the decoding result by the selected processing section as a decoded pixel block. <P>COPYRIGHT: (C)2003,JPO</p>
申请公布号 JP2003189304(A) 申请公布日期 2003.07.04
申请号 JP20010386151 申请日期 2001.12.19
申请人 AKUSERU:KK 发明人 SHIBATA TAKAYUKI
分类号 H04N11/04;H03M7/30;H04N1/41;H04N19/42;H04N19/423;H04N19/44;H04N19/59;H04N19/60;H04N19/91;H04N19/93;(IPC1-7):H04N7/30 主分类号 H04N11/04
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