| 摘要 |
PURPOSE: A planarization method of a semiconductor device is provided to be capable of preventing processing failure due to the thickness difference of an interlayer dielectric. CONSTITUTION: A plurality of metal patterns(22) are formed on a semiconductor substrate(21). Fine insulating particles(23) are filled between the metal patterns(22) by using sol-gel technique. The insulating particles(23) are planarized by polishing. Then, an insulating layer(24) is formed on the entire surface of the resultant structure. At this time, PETEOS(Plasma Enhanced Tetra Ethyl Ortho Silicate) is used as the insulating layerA(24).
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