发明名称 SYSTEM FOR CLOCK SYNCHRONIZATION BETWEEN DUPLEXING SWITCH BOARDS AND LINE CONNECTION BOARDS
摘要 PURPOSE: A system for clock synchronization between duplexing switch boards and line connection boards is provided to select synchronous clocks of an active switch board in each line connection board according to control signals outputted from the switch boards, thereby implementing clock synchronization between the duplexing switch boards and each of the line connection boards. CONSTITUTION: Each of switch boards(210,220) comprises as follows. Switching units(211,221) perform switching processes, generate control signals showing duplexing states by exchanging duplexing control signals between the switch boards(210,220), and output the control signals to many line connection boards(230,240). Clock circuits(212,222) generate synchronous clocks by using predetermined synchronous reference clocks, and output the synchronous clocks to the line connection boards(230,240). Each of the line connection boards(230,240) comprises as follows. Synchronous clock selectors(231,241) receive the control signals and the synchronous clocks, decide the control signals of each of the switch boards(210,220), and select synchronous clocks outputted from an active switch board. Interface functional units(232,242) perform line interfacing processes by using the selected synchronous clocks.
申请公布号 KR20030055375(A) 申请公布日期 2003.07.04
申请号 KR20010084082 申请日期 2001.12.24
申请人 ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE 发明人 LEE, HYEONG HO;LEE, HYEONG SEOP;LEE, SANG U
分类号 H04L12/50;(IPC1-7):H04L12/50 主分类号 H04L12/50
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