发明名称 |
CHIP AND WAFER INTEGRATION PROCESS USING VERTICAL CONNECTIONS |
摘要 |
A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate (1). A metallized feature (2) is formed in the top surface of a substrate, and a handling plate (35) is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via (20). The substrate may comprise a chip (44) having a device (30), e.g. a PE chip. The plate may be a wafer (65) attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices (30,60) fabricated therein, so that the process provides vertical wafer-level integration of the devices. |
申请公布号 |
WO03054956(A1) |
申请公布日期 |
2003.07.03 |
申请号 |
WO2002US38355 |
申请日期 |
2002.11.26 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
POGGE, BERNHARD, H.;YU, ROY;PRASAD, CHANDRIKA;NARAYAN, CHANDRASEKHAR |
分类号 |
H01L23/12;H01L21/68;H01L21/768;H01L23/48;H01L23/485;H01L23/525;H01L25/065;H01L25/07;H01L25/18 |
主分类号 |
H01L23/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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