| 摘要 |
A circuit arrangement for testing an analog-digital converter (2) which provides a quick test result and which is less susceptible to operational errors. The individual digital outputs of the analog-digital converter (2) are combined in a combinatorial mathematical mode (4) in such a way that only one output signal arises. Said output signal is a rectangular function. The ascending and descending flanks mark the switching points. Said output signal is associated with an individual test pin (6). A test routine is then carried out, determining the instantaneous digital output value for each switching point by means of a data bus (8) and is filed in a respective register. A I<2>C bus can, for instance, be used as a data bus (8).
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