发明名称 |
FULL RAIL DRIVE ENHANCEMENT TO DIFFERENTIAL SEU HARDENING CIRCUIT |
摘要 |
A hardening circuit is provided for an integrated circuit which includes a data state reinforcing feedback path having a data node Q and a data complement node QN. A first hardening transistor is coupled between a rail and the data node Q, and a second hardening transistor coupled between the rail and the data complement node QN. The first and second hardening transistors provide additional drive to the data node Q and the data complement node QN. Gate controls operate the first and second hardening transistors and provide full rail drive to SEU sensitive nodes.
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申请公布号 |
US2003122602(A1) |
申请公布日期 |
2003.07.03 |
申请号 |
US20010034808 |
申请日期 |
2001.12.28 |
申请人 |
TA THEODORE T.;GOLKE KEITH W. |
发明人 |
TA THEODORE T.;GOLKE KEITH W. |
分类号 |
G11C11/412;(IPC1-7):H03K3/037 |
主分类号 |
G11C11/412 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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