发明名称 Method and apparatus for clock and power control in wireless systems
摘要 A digital baseband processor is provided which receives a system clock generated by a system oscillator and generates a plurality of clock signals from the system clock. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and other modules which may require one of the plurality of clock signals for operation. The digital baseband processor also includes a power management circuit which may power down the system oscillator when modules such as the digital signal processor and microcontroller do not require clock signals derived from the system oscillator. The power management circuit may gate off clock signals to modules when those modules do not require clock signals, without powering down the system oscillator.
申请公布号 US2003126487(A1) 申请公布日期 2003.07.03
申请号 US20020230534 申请日期 2002.08.29
申请人 SOERENSEN JOERN;ANAND HITESH;ALLEN MICHAEL S. 发明人 SOERENSEN JOERN;ANAND HITESH;ALLEN MICHAEL S.
分类号 G06F9/30;G06F1/04;G06F1/08;G06F1/32;G06F9/38;G06F9/46;G06F9/48;G06F11/28;G06F11/36;G06F12/00;G06F12/02;G06F12/08;G06F13/28;G06F13/38;G06F13/42;H03L7/08;H03L7/095;H03L7/183;H04B1/40;(IPC1-7):G06F1/26 主分类号 G06F9/30
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