发明名称 Method to avoid via poisoning in dual damascene process
摘要 A method of forming a semiconductor device is described comprising forming a first patterned conductive layer on a dielectric on a substrate. A first barrier layer comprising silicon nitride is formed on the surface of the first patterned conductive layer, followed by forming a second barrier layer comprising silicon carbide on the surface of the first barrier layer. Using standard lithographic techniques a via and a trench are formed to the surface of the conductive layer.
申请公布号 US2003124836(A1) 申请公布日期 2003.07.03
申请号 US20020040224 申请日期 2002.01.02
申请人 ANDIDEH EBRAHIM 发明人 ANDIDEH EBRAHIM
分类号 H01L21/768;(IPC1-7):H01L21/476 主分类号 H01L21/768
代理机构 代理人
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