High level synthesis method and apparatus

摘要

A behavioral description is converted to a CDFG. The CDFG is scheduled in such a way that the number of registers is minimized with a desired number of clock cycles. Hardware is allocated to the scheduled results. The minimum clock period (semi-synchronous minimum clock period) attainable by adjusting clock timings for allocated registers is determined. When the semi-synchronous minimum clock period is greater than a desired clock period, all the clock timings are reset to a same value and then the positions of the registers in the CDFG are so changed as to reduce the clock period. The processing returns to the step of determining the semi-synchronous minimum clock period when the performance is improved as a result of performing retiming, or otherwise is terminated.