| 摘要 |
The present invention provides a system for reducing power consumption in a memory device containing a memory array having a number of memory cells. The present invention raises a supply voltage of a row of memory cells from a first voltage to a second voltage whenever the row of memory cells is selected for access (102) and lowers the supply voltage of the row of selected memory cells from the second voltage to the first voltage after the row of selected memory cells has been accessed (106). The first voltage is low enough to reduce power consumption of the memory device, but is high enough to retain data stored in the memory device. The second voltage is a nominal operating voltage sufficient to access the row of selected memory cells while maintaining the performance and stability of the row of selected memory cells.
|
