| 摘要 |
A semiconductor device manufacturing process is disclosed which includes a test process capable of minimizing the test time for a single wafer, thus capable of reducing the test cost and improving the throughput. A test system is used in the semiconductor device test process. The test system is made up of a wafer which comprises plural chips formed with flash memories, a wafer level whole-surface contact device for contact with the whole surface of the wafer, a tester for testing electric characteristics of the wafer, and a BOST board interposed between the tester and the wafer level whole-surface contact device and with chip-by-chip control circuits mounted thereon. In the case where the test time differs depending on each chip in the wafer, the BOST board controls each test item for each chip so that in a parallel manner for the chips, upon completion of a preceding test, a shift is made to the next test.
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