Output buffer circuit, memory chip, and semiconductor device having a circuit for controlling buffer size

摘要

An output buffer circuit including a programmable impedance buffer configured to match a buffer size thereof with an external impedance, a buffer size decision circuit configured to generate a plurality of buffer size signals for determining the buffer size of the programmable impedance buffer synchronized with a first clock signal, and an impedance adjustment circuit configured to adjust the buffer size based on the buffer size signals in response to a level of an output data signal.