发明名称 |
All-digital symbol clock recovery loop for synchronous coherent receiver systems |
摘要 |
A symbol clock (16) associated with a symbol stream (5) in a synchronized communication receiver can be recovered by adjusting the phase of a symbol clock signal (12). The phase adjustment is accomplished by applying a digitally controlled delay (13) to the symbol clock signal based on a timing relationship between the symbol clock and symbol transitions (17) in the symbol stream.
|
申请公布号 |
US2003123571(A1) |
申请公布日期 |
2003.07.03 |
申请号 |
US20020225837 |
申请日期 |
2002.08.22 |
申请人 |
SCHEFFLER BERND |
发明人 |
SCHEFFLER BERND |
分类号 |
H03L7/081;H03L7/089;H04L7/033;H04L27/156;(IPC1-7):H04L27/06;H04L7/00 |
主分类号 |
H03L7/081 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|