发明名称 |
Apparatus and method for M-ary demodulation in a digital communication system |
摘要 |
A demodulator for demodulating a set of S possible orthogonal modulation codes received serially as binary data, wherein each of the orthogonal modulation codes comprises M binary bits representing an N-bit data symbol and wherein M=2N. The demodulator comprises: 1) a Logic 0 input detector for comparing each of the M binary bits of the serially received orthogonal modulation codes to a Logic 0 and outputting a +1 signal if a match occurs and outputting a -1 signal if a match does not occur; 2) a summation circuit comprising S accumulators; 3) a Logic 0 switch array comprising S switches, wherein a Kth one of the S switches in the Logic 0 switch array couples an output of the Logic 0 input detector to a first input of a Kth one of the S accumulators; 4) a storage array for storing the S orthogonal modulation codes; and 5) control circuitry for synchronously applying the M bits in a Kth one of the S orthogonal modulation codes in the storage array as a switch control signal to the Kth switch in the Logic 0 switch array so that each Logic 0 binary data in the Kth orthogonal modulation code closes the Kth switch in the Logic 0 switch array, thereby connecting the output signal of the Logic 0 input detector to the first input of the Kth accumulator.
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申请公布号 |
US2003123577(A1) |
申请公布日期 |
2003.07.03 |
申请号 |
US20010038869 |
申请日期 |
2001.12.31 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
CLEVELAND JOSEPH ROBERT |
分类号 |
H04B1/707;H04J11/00;H04L1/00;H04L27/20;(IPC1-7):H04L27/06 |
主分类号 |
H04B1/707 |
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