| 摘要 |
An integrated circuit wafer, covered by a protective overcoat, comprising an array of integrated circuit chips bordered by seal regions and separated by dicing lines; at least two sets of substantially parallel structures within each of said seal regions, each set extending along the edge of a chip on opposite sides of each said dicing line, respectively; each of said sets comprising at least one continuous barrier wall adjacent each chip, respectively; at least one sacrificial composite structure in combination therewith, between said wall and the center of said dicing line, said composite structure being a discontinuous barrier wall comprising metal rivets interconnecting electrically conductive layers in an alternating manner, whereby said composite structure provides mechanical strength to said sets and simultaneously disperses the energy associated with crack propagation; and at least one slot opened into said protective overcoat, reaching from the surface of said overcoat at least to the surface-nearest electrically conductive layer of said composite structure, whereby cracks propagating in said protective overcoat will be stopped. |
