| 摘要 |
PURPOSE: A multi-plane block address resistor is provided to increase the program/erasing speed of a chip by storing a block address inputted to a plane on a register to simultaneously perform a programming and erasing operation. CONSTITUTION: A plane decoder(10) decodes a plurality of plane address signals to output plural plane signals for enabling a selected plane. A plurality of block address register groups(21 - 2Nop) are enabled by the plane signal, stores a block address signal inputted by a latched block address signal, and outputs the plane signal and the block address signal. The block address register groups(21 - 2Nop) are initialized by a reset signal. A plane resistor outputs a latched plane signal and a latch block enable signal. A plurality of block address registers store the plurality of address signals according to the plane signal and the latch block enable signal to output them.
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