发明名称 METHOD FOR FORMING BIT LINE OF SEMICONDUCTOR DEVICE
摘要 PURPOSE: A method for forming a bit line of a semiconductor device is provided to prevent the short circuit between a bit line and other lines by forming a nitride layer around the bit line. CONSTITUTION: A gate insulating layer, a gate electrode(9), and a mask nitride layer(10a) are formed on a silicon substrate(6) including a field oxide layer(7). A word line is formed by patterning partially the mask nitride layer, the gate electrode, and the gate insulating layer. A source/drain region(11) is formed on the silicon substrate of the outside of the word line and a nitride layer spacer(10b) is formed on a sidewall of the word line. The source/drain region is exposed by a wet etch method. A bit line contact plug(12) and a storage node contact plug(13) are simultaneously formed thereon. The first oxide layer(14) is formed between the word lines. The first oxide layer is planarized by a CMP(Chemical Mechanical Polishing) process or an etch-back process. A nitride layer(10c) is formed on the first oxide layer. The second oxide layer(15) is stacked on the entire surface of the resultant and a bit line contact mask pattern is formed thereon. The second oxide layer is etched by using the bit line contact mask pattern. The bit line contact mask pattern is removed therefrom. A nitride layer spacer(16) is formed by filling a nitride layer into a contact hole of the second oxide layer. A bit line material layer(17) is stacked on the resultant and a blanket etch-back process and the CMP process are performed. A bit line is formed by filling and etching a capping nitride layer(18) into the bit line material layer. A capping oxide layer(19) is formed on the resultant.
申请公布号 KR20030053965(A) 申请公布日期 2003.07.02
申请号 KR20010084013 申请日期 2001.12.24
申请人 DONGBU ELECTRONICS CO., LTD. 发明人 PARK, CHEOL SU
分类号 H01L21/3205;(IPC1-7):H01L21/320 主分类号 H01L21/3205
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