发明名称
摘要 PURPOSE: A parallel mount test board for semiconductor memory device is provided to prevent an operation error of a multi-bank and a damage of a socket by using a reference slot and an extension slot. CONSTITUTION: A parallel mount test board includes an extension slot(35), a reference slot(34), and a plurality of parallel test slots(36,38). The parallel test slots(36,38) are connected with the extension slot(35) and the reference slot(34) in parallel. A plurality of memory elements are inserted into the extension slot(35), the reference slot(34), and the parallel test slots(36,38). Read/write operations are performed in the parallel test slots(36,38) when the read/write operation is performed in the reference slot(34). The reference slot(34) and the parallel test slots(36,38) are influenced by timing twisted by the extension slot(35).
申请公布号 KR100389804(B1) 申请公布日期 2003.07.02
申请号 KR20010028955 申请日期 2001.05.25
申请人 发明人
分类号 H01L21/66 主分类号 H01L21/66
代理机构 代理人
主权项
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