| 摘要 |
<p>PURPOSE: A pipe latch control circuit of a synchronous memory is provided to prevent the error operation of the synchronous memory by restraining the loss of data access time. CONSTITUTION: A plurality of count stages respond to a data output buffer driving signal(clk_do) to perform a sequential count operation. A count signal driving unit(42) is controlled by the data output buffer driving signal(clk_do) to drive each count signal outputted from the plurality of count stages and to generate a pipe output control signal(poutz<0:3>). A first count stage of the plurality of count stages includes an initial count signal generating unit(40) for generating an initial count signal in response to a counter reset signal(rstdoutz). The initial count signal generating unit(40) includes a plurality of latching units for latching each count signal in response to the data output buffer driving signal(clk_do).</p> |
