发明名称 Circuits and methods for sampling an input signal in a charge redistribution digital to analog converter
摘要 A method and a circuit of performing an analog to digital conversion in a charge redistribution circuit including a capacitor array of weighted capacitors and a transistor track switch for sampling an input signal into the capacitor array. A common mode voltage is stepped to a voltage sufficient to turn on the transistor track switch during a sampling phase. During the sampling phase, a top plate of each of the capacitors is coupled to the common mode voltage through the track switch while the bottom plate of each of the capacitors is coupled to an input to sample an input signal. During a conversion phase, the top plate of each of the capacitors is decoupled from the common mode voltage and the bottom plates of a selected one of the weighted capacitors is coupled to a first reference voltage, a weight of the selected one of the weighted capacitors proportional to the step in the common mode voltage. The bottom plates of the remaining capacitors are coupled to a second reference voltage and the top plate of the weighted capacitors compared against a comparison voltage proportional to the step in the common mode voltage. If the top plate voltage is above the comparison voltage, then the selected capacitor is coupled to a second reference voltage.
申请公布号 US6587066(B1) 申请公布日期 2003.07.01
申请号 US20020052607 申请日期 2002.01.18
申请人 CIRRUS LOGIC, INC. 发明人 SOMAYAJULA SHYAM S
分类号 H03M1/06;H03M1/46;H03M1/80;(IPC1-7):G08C19/12;H03M1/12;H03M1/10 主分类号 H03M1/06
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