发明名称 Etch resistant shallow trench isolation in a semiconductor wafer
摘要 A shallow isolating trench is formed in a semiconductor wafer between active component areas to electrically isolate the active components from each other. The isolating trench is primarily formed of an insulating material, such as an oxide, in a recess formed into the wafer. An etch resistant material, such as BTBAS nitride, is placed over the insulating material in the recess. The etch resistant material protects the insulating material from erosion due to subsequent semiconductor fabrication process steps, so the integrity of the isolating trench and the planarity of the wafer are generally maintained.
申请公布号 US6586814(B1) 申请公布日期 2003.07.01
申请号 US20000735084 申请日期 2000.12.11
申请人 LSI LOGIC CORPORATION 发明人 PATEL RAJIV;CHAN DAVID;KAMATH ARVIND;RAFFTESAETH KEN;GOPINATH VENKATESH P.
分类号 H01L21/762;(IPC1-7):H01L29/00 主分类号 H01L21/762
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