发明名称 FAULT-TOLERANT ADDRESS LOGIC FOR SOLID STATE MEMORY
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a fault-tolerant address logic in which access can be performed for a main memory even when some address line can not be used, in a method addressing a solid state memory having address logic. <P>SOLUTION: In a method addressing a solid state memory having address logic, a set of address elements is set by making (t) having address logic as the maximum allowable number of defective address lines and by allotting a set of address setting having symmetric distance of at least (t+1). This address setting can be assumed to that t-Sperner(n, L) code word, constant weight code (CWC) word, humming distance between arbitrary two address setting having same weight is at least 2t+2. <P>COPYRIGHT: (C)2003,JPO</p>
申请公布号 JP2003178595(A) 申请公布日期 2003.06.27
申请号 JP20020300375 申请日期 2002.10.15
申请人 HEWLETT PACKARD CO 发明人 HOGAN JOSH;ROTH RON M
分类号 G11C17/00;G11C8/10;G11C17/06;G11C17/16;G11C29/00;G11C29/04;(IPC1-7):G11C29/00 主分类号 G11C17/00
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