CIRCUIT AND METHOD FOR GENERATING OUTPUT CLOCK SIGNAL HAVING CONTROLLED TIMING

摘要

PURPOSE: A circuit and a method for generating an output clock signal having the controlled timing are provided to reduce the effective unit delay by using a phase blending n additional variable delay line to generate a signal with an intermediate phase. CONSTITUTION: The first delay circuit(203) receives an input clock signal and generates the first delayed input clock signal. The second delay circuit(205) receives the input clock signal and generates the second delayed input clock signal. A phase blending circuit(207) receives the first and the second delayed input clock signals and outputs a phase blending clock signal by blending phases of the first and the second delayed input clock signals. A phase detection circuit(209) receives a reference clock signal and the phase blending clock signal and generates selectively a phase push signal and a phase pull signal. A delay control circuit(211) receives the phase push signal or the phase pull signal and generates selectively the first and the second delay control signals.