发明名称 |
MASK LAYER AND INTERCONNECTION STRUCTURE FOR MANUFACTURING DUAL DAMASCENE SEMICONDUCTOR |
摘要 |
PROBLEM TO BE SOLVED: To provide a mask layer and an interconnection structure for manufacturing a dual damascene semiconductor. SOLUTION: A new mask layer 37 is used for dual damascene formation of an interconnection structure for an integrated circuit device. The interconnection structure has low-k dielectric materials 31 and 32. The mask layer 37 has a passivation thin film 38 which is deposited on the low-k dielectric materials 31 and 32. A barrier thin film 39 is deposited on the passivation thin film 38 and a metal thin film 40 is deposited on the barrier thin film 39. The metal thin film 40 increases the total etch selectively with respect to the mask layer 37 in order to assure faithful transfer of the shape of a via 44 and a trench 42 to the low-k dielectric materials 31 and 32 during the dual damascene process. COPYRIGHT: (C)2003,JPO
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申请公布号 |
JP2003179136(A) |
申请公布日期 |
2003.06.27 |
申请号 |
JP20020280601 |
申请日期 |
2002.09.26 |
申请人 |
AGERE SYSTEMS INC |
发明人 |
OLADEJI ISAIAH O;JESSEN SCOTT;TAYLOR JOSEPH ASHLEY |
分类号 |
H01L21/3065;H01L21/311;H01L21/56;H01L21/768;H01L23/495;H01L23/522;H01L23/532;(IPC1-7):H01L21/768;H01L21/306 |
主分类号 |
H01L21/3065 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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