| 摘要 |
PURPOSE: A method for manufacturing a semiconductor memory device is provided to be capable of easily levelling the semiconductor memory device and overcoming the step difference between an align key region, a logic region, and a DRAM cell region by carrying out a CMP(Chemical Mechanical Polishing) process on the second interlayer dielectric. CONSTITUTION: The first align keys(44) of a logic region and contact holes(46) of a DRAM cell region, are formed by patterning the first interlayer dielectric(42) formed on a semiconductor substrate(40). A lower conductive layer pattern(48) and a lower electrode(50) are formed on the resultant structure. An upper conductive pattern(52) and an upper electrode(54) are formed on the lower conductive layer pattern and the lower electrode, respectively. After forming the second interlayer dielectric(56) on the resultant structure, the interlayer dielectric is selectively etched by using a photoresist pattern as a mask. After removing the photoresist pattern, a CMP process is carried out for levelling the second interlayer dielectric.
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