发明名称 |
METHOD FOR MANUFACTURING INTEGRATED CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit by a double-damascene process which exhibits a wide process flexibility and can be easily adapted in mass-production process. SOLUTION: After an etch stop layer 54 is patterned for forming an opening 72 corresponding to a pattern in a connection which is formed on the first level of a two-level connection structure, an intermetallic dielectric layer 58 is provided on it and a photoresist mask 62 is provided on it. Openings 64 and 66 of the mask 62 correspond to the wiring pattern provided on the second level of the connection structure and a dielectric layer 58 is partially exposed from them. The dielectric layer 58 is etched and the etching is advanced in such a way that an opening 68 is produced in the exposed part of the stop layer 54 from the opening 72 of the interlayer dielectric layer 52. In other words, openings for both of the wiring on the second level and the connection on the first level are demarcated by a single etching process. Further, the opening 72 of the stop layer is tapered with its upper diameter being larger than its lower diameter. COPYRIGHT: (C)2003,JPO
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申请公布号 |
JP2003179140(A) |
申请公布日期 |
2003.06.27 |
申请号 |
JP20020358268 |
申请日期 |
2002.12.10 |
申请人 |
UNITED MICROELECTRONICS CORP |
发明人 |
YEW TRI-RUNG;RYU MOSHO;RO KATETSU;SUN SHIH-WEI |
分类号 |
H01L21/3065;H01L21/768;(IPC1-7):H01L21/768;H01L21/306 |
主分类号 |
H01L21/3065 |
代理机构 |
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