| 摘要 |
PURPOSE: A DLL(Delay Locked Loop) circuit is provided to improve a time for setting a new lock-in state by maintaining an enable state of a low pass filter. CONSTITUTION: A DLL circuit includes a delay chain portion(22), a shift register portion(23), a phase comparison portion(21), a shift control portion(24), and a low pass filter portion(25). The delay chain portion delays a reference clock and generates an output clock. The shift register portion controls a clock delay time of the delay chain portion according to a stored register value. The phase comparison portion generates the first shift signal and a lock-in release signal by comparing the reference clock to a phase of a feedback clock of the output clock. The shift control portion determines a state of lock-in by using the shift signal and the lock-in release signal. The shift control portion generates a delay locked signal if the state is lock-in state, and transfers the first shift signal to the shift register portion if not. The low pass filter portion generates the second shift signal by using the first shift signal when receiving the delay locked signal.
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