发明名称 BAND WIDTH MATCHING METHOD FOR SCAN ARCHITECTURE IN INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a method for performing a test to be conducted on an IC with the possibility of resetting one of scan architectures and with a high degree of accuracy and failure detection range and in the shortest time. SOLUTION: With respect to the method for setting an integrated circuit (200), which is provided with several integrated circuit input/output pins having specified maximum input/output frequency and several scan chains (208) which are electrically conductive with the input/output pins for a test, the scan chains have the specified maximum latching frequency and the integrated circuit is connected to an integrated circuit testing device via a usable number of pins of the several integrated circuit input/output pins. The method includes a step for setting the time for testing the integrated circuit to the shortest when the latch frequency is lower than the specified maximum input/output frequency and the number of available integrated circuit input/output pins is smaller than that, which is required by the presented scan architecture (202). COPYRIGHT: (C)2003,JPO
申请公布号 JP2003179149(A) 申请公布日期 2003.06.27
申请号 JP20020259142 申请日期 2002.09.04
申请人 AGILENT TECHNOL INC 发明人 KHOCHE AJAY;RIVOIR JOCHEN;ARMSTRONG DAVID H
分类号 G01R31/28;G01R31/3185;H01L21/822;H01L27/04;(IPC1-7):H01L21/822 主分类号 G01R31/28
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