| 摘要 |
PURPOSE: A delay locked loop circuit for improving a jitter characteristic is provided to improve the final jitter characteristic and a maximum phase error by using two phase detection circuits and two delay circuits. CONSTITUTION: A delay locked loop circuit includes a delay circuit(605,607), a phase detection block(601,603), and a delay control circuit. The delay circuit receives an input clock signal and a delayed output clock signal. The phase detection block receives the input clock signal and the output clock signal of the delay circuit. The phase detection block generates a phase pull signal when a phase of the input clock signal delayed as much as one hour precedes a phase of the output clock signal or a phase push signal when the phase of the input clock signal delayed as much as two hours does not precede the phase of the output clock signal. A delay control circuit generates a delay control circuit according to the phase pull signal or the phase push signal.
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