| 摘要 |
<p>PURPOSE: To provide a PLL circuit in which a phase error is reduced into a negligible level. CONSTITUTION: VDLs 1I and 1R delay an input clock ICLK and a feedback clock RCLK and apply a delayed input clock DICLK and a delayed feedback clock DRCLK to a PLL part 10. The PLL part 10 receives the delayed input clock DICLK and the delayed feedback clock DRCLK and outputs a PLL output OUTP to synchronize these signals. The PLL output OUTP is finally fed back through an external circuit as a feedback clock RCLK. A PD 3 detects the phase difference of the input clock ICLK and the feedback clock RCLK and outputs a phase comparing signal SPD. On the basis of the phase comparing signal SPD, a control logic circuit 2 judges the advancement of the phase of the feedback clock RCLK relative to the input clock ICLK and controls a delay time DT of the VDL 1R so that the phase error of the input clock ICLK and the feedback clock RCLK can become zero.</p> |
