| 摘要 |
Disclosed is an RSA cryptographic processing apparatus capable of performing the fast operating function. A modular multiplication operation or a modular exponentiation operation, i.e., an RSA cryptographic operation, is selectively performed according to a control signal inputted, the modular operation of the data of 512 to 1024 bits is iteratively performed by use of 32-bit operating unit, and the data of 512 to 1024 bits is operated by use of a 32-bit operating unit, thereby minimizing the size of the register storing the data and reducing the size of the cryptographic apparatus, and which the intermediate value generated at the operation process is stored in the internal register instead of the memory, thereby minimizing the times of access to the memory.
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