| 摘要 |
A semiconductor testing apparatus capable of reducing time required for testing or remedying a plurality of semiconductor devices. The semiconductor testing apparatus performs test for a plurality of DUT (9) in parallel and performs remedy for the plurality of DUT (9) in parallel. For this, the apparatus includes an ALPG (1), a PDS (2), an AFM (3), a driver pin processor (4), an IO pin processor (5), a driver channel (6), and an IO channel (7). The IO pin processor (5) has a plurality of sub-FC units (58). When test is performed simultaneously for a plurality of DUT (9), an individual pattern waveform is generated corresponding to individual information.
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