发明名称 |
Multiple supply-voltage zipper CMOS logic family with low active leakage power dissipation |
摘要 |
An embodiment zipper circuit achieves reduced leakage current by utilizing four voltages so that FETs in the p-logic blocks and n-logic blocks are reversed biased during a pre-charge phase. The FETs in a logic block are also reversed biased during an evaluation phase if the input voltages to the logic block are such that the logic block is not driven ON during the evaluation phase.
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申请公布号 |
US2003117179(A1) |
申请公布日期 |
2003.06.26 |
申请号 |
US20010027292 |
申请日期 |
2001.12.20 |
申请人 |
HSU STEVEN K.;KRISHNAMURTHY RAM |
发明人 |
HSU STEVEN K.;KRISHNAMURTHY RAM |
分类号 |
H03K19/096;(IPC1-7):H03K19/096 |
主分类号 |
H03K19/096 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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