| 摘要 |
<p>A memory cell capacitor (C3) of a DRAM is fabricated by using an MIM capacitor in which a metal wiring line in the same layer (M3) as that of the metal wiring line in a logic circuit (LOGIC) is used as an electrode, so that the process cost can be lowered. The capacitor is formed of a high dielectric constant material in a layer above a wiring layer where a bit line (BL) is formed, thereby the integration is enhanced. A 2T cell is used, so that a sufficient signal quantity can be ensured even if the capacitor is operated on a low voltage. The capacitor forming processes of an analog (ANALOG) and a memory (MEM) are made common, so that a semiconductor integrated circuit in which the logic, analog and memory are mounted on one chip can be realized at a low cost.</p> |
