| 摘要 |
PURPOSE: A parity error detection circuit is provided to stably detect by synchronizing with the clock with implementing the parity check in a further rapid time in comparison with a conventional method. CONSTITUTION: A parity error detection circuit includes a first NAND gate(21) for outputting by logically calculating the external receive signal and the feedback signal, a first XOR gate(22) for outputting by logically calculating the inputted data signal and the output signal of the first NAND gate(21), a shift register(23), a second XOR gate(24), a second NAND gate(25) and an inverter(26) for outputting the final output signal by inverting the output signal of the second NAND gate(25). The second XOR gate receives the output signal of the second XOR gate(24) and the first input signal to determine the parity inputted from the outside and outputs the received signal by being logically calculated. The second NAND gate(25) receives the output signal of the second XOR gate(24) the second input signal to determine the parity inputted from the outside and outputs the received signal by being logically calculated.
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