发明名称 Semiconductor device having a trench isolation and method of fabricating the same
摘要 The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask (RM12) is formed so as to have an opening over a region (PR) in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film (PT11) and a peak of an impurity profile is generated in an SOI layer (3), thereby forming a channel stop layer (N1) in the SOI layer (3) under the partial isolation oxide film (PT11), that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer (N1) is set to 1x1017 to 1x1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer (3) corresponding to the active region (AR).
申请公布号 US2003119245(A1) 申请公布日期 2003.06.26
申请号 US20020237022 申请日期 2002.09.09
申请人 发明人 IWAMATSU TOSHIAKI;IPPOSHI TAKASHI;MATSUMOTO TAKUJI;MAEDA SHIGENOBU
分类号 H01L21/76;H01L21/336;H01L21/762;H01L21/84;H01L27/08;H01L27/12;H01L29/786;(IPC1-7):H01L21/823 主分类号 H01L21/76
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