发明名称 Design method for integrated circuit chips
摘要 A method of placing integrated circuit chips on a wafer uses a library of average delay time values of logic gates. Exposure-dependent delay time values of the logic gates, which result from exposure of a unit area to a beam of radiation, are additionally stored in the library. These delay time values are detected by successively exposing unit areas of a test wafer to a beam of radiation as a function of relative positions of each integrated circuit chip within the unit exposure area. In a modified embodiment, only one integrated circuit chip within each unit area is exposed to the radiation beam, and the exposure-dependent delay time values are detected as a function of position within the exposed integrated circuit chip or as a function of distance from the center of the each unit area.
申请公布号 US2003121014(A1) 申请公布日期 2003.06.26
申请号 US20020326379 申请日期 2002.12.23
申请人 NEC ELECTRONICS CORPORATION 发明人 GOTO JUNICHI
分类号 G03F7/20;G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G03F7/20
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